1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, and more specifically to a semiconductor device having a contact hole and a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In recent years, as the semiconductor devices has undergone further miniaturization, the distance between the electrodes formed on a surface of a semiconductor substrate has become smaller. In addition, between those electrodes, the amount of margin in the distance between an electrode and a contact hole formed in an interlayer insulating film is also becoming smaller.
Accordingly, technologies relating to the so-called self-aligned contact hole is being developed in which an etching stopper such as a nitride film is formed to cover a gate electrode, and in which a contact hole is not allowed to reach the gate electrode even when the contact hole and the gate electrode overlap in a planar manner. For instance, a semiconductor device having a contact hole formed in a self-aligned manner is described in Japanese Patent Laying-Open No. 9-134956.
FIG. 23 is a cross sectional view of a conventional semiconductor device described in the above publication. As seen in FIG. 23, an element isolating region 514 is formed on a surface of a semiconductor substrate 513. In addition, a conductive region 513a is formed in the part of the surface of semiconductor substrate 513 where element isolating region 514 is not formed.
An interconnection 516 is formed on semiconductor substrate 513 with a gate insulating film 515 interposed therebetween. A silicon oxide film 517 is formed on interconnection 516, and sidewalls 518 are formed in contact with interconnection 516.
Further, an oxide film 519 and an etching stopper film 520 are formed covering element isolation region 514, sidewalls 518, and silicon oxide film 517. Etching stopper film 520 consists of an insulating film containing nitrogen molecules such as a silicon nitride film.
An interlayer insulating film 521 is formed covering etching stopper film 520. In interlayer insulating film 521, a hole reaching conductive region 513a is formed. A contact 522 is formed within the hole. An upper-layer interconnection 523 is formed in contact with contact 522.
When manufacturing such a semiconductor device, oxide film 519 and etching stopper film 520 are formed to cover interconnection 516, silicon oxide film 517, and sidewalls 518. Interlayer insulating film 521 is formed to cover etching stopper film 520, and then a hole reaching conductive region 513a is formed in interlayer insulating film 521. At this time, interlayer insulating film 521 is etched with the condition that the etching rate of interlayer insulating film 521 is greater than the etching rate of etching stopper film 520. Therefore, a portion of etching stopper film 520 where it is thick in the vertical direction, i.e. the portion of etching stopper film 520 having a large thickness in the vertical direction where etching stopper film 520 is formed along sidewalls 518, is not etched easily. As a result, the etching of sidewalls 518 can be prevented so that the hole will only reach conductive region 513a even when a large hole is formed, and is less likely to reach sidewalls 518 and interconnection 516.
Thus, a hole can be formed without allowing the hole to reach interconnection 516 even when the margin of the distance between the hole and interconnection 516 is small.
The problems that arise in a conventional semiconductor device as shown in FIG. 23 will be described below.
Recently, researches are made in relation not only to the miniaturization but also to a higher-speed operation of a semiconductor device. In order to increase the operating speed of a semiconductor device, there is a need to reduce the contact resistances between various conductive layers formed in a semiconductor device. Further, the electric resistance of a conductive layer itself needs to be reduced.
A problem involved in a conventional semiconductor device as shown in FIG. 23 is that the contact resistance between contact 522 and conductive region 513a is too high to achieve a high-speed operation of the semiconductor device.
Moreover, the cross section of upper-layer interconnection 523 must be made larger in order to reduce the electric resistance of upper-layer interconnection 523. For this purpose, the width or the thickness of upper-layer interconnection 523 might be increased. If the width of upper-layer interconnection 523 is increased, however, the semiconductor device cannot be miniaturized. Moreover, if the thickness of upper-layer interconnection 523 is increased, the evenness of the semiconductor device cannot be ensured. Therefore, conventionally, it was too difficult to enlarge the cross section of upper-layer interconnection 523 that a higher-speed operation of the semiconductor device could not be achieved.
Thus, the present invention is made to solve the above-described problems. An object of the present invention is to provide a semiconductor device capable of a high-speed operation and having a small contact resistance between two conductive regions as well as to provide a method of manufacturing such a semiconductor device.
Moreover, another object of the present invention is to provide a semiconductor device capable of a high-speed operation with a conductive layer having a small electric resistance as well as to provide a method of manufacturing such a semiconductor device.
A semiconductor device according to one aspect of the present invention is provided with a semiconductor substrate, a pair of low concentration impurity regions, a gate electrode, a protective film, an interlayer insulating film, a high concentration impurity region, and a conductive layer. Low concentration impurity regions having a relatively low impurity concentration are formed spaced apart from one another on a surface of the semiconductor substrate. The gate electrode is formed between the pair of low concentration impurity regions on the semiconductor substrate with a gate insulating film interposed between the gate electrode and the semiconductor substrate. The protective film covers the gate electrode. The interlayer insulating film covers the gate electrode and the protective film, and has a hole reaching an impurity region. The etching rate of the interlayer insulating film is greater than that of the protective film when a prescribed etchant is employed. The high concentration impurity region is formed by implanting an impurity into the semiconductor substrate through a hole, and has a relatively high impurity concentration within a low concentration impurity region. The conductive layer fills the hole such that it is electrically connected to the high concentration impurity region.
In a semiconductor device thus configured, the high concentration impurity region is formed by implanting an impurity into the semiconductor substrate through a hole so that the bottom of the hole forms the high concentration impurity region. Since the conductive layer is provided to fill the hole such that an electrical connection to the high concentration impurity region is established, the conductive layer is electrically connected to the impurity region that has a relatively high impurity concentration. Thus, the hole and the surface of the high concentration impurity region that is connected through the hole do not shift out of position. Therefore, an increase in the contact resistance between the conductive layer and the high concentration impurity region can be prevented, and a high-speed operation of the semiconductor device is achieved.
Preferably, the protective film includes a nitride film and the interlayer insulating film includes an oxide film.
Moreover, the protective film preferably is at least one of a silicon oxynitride film (SiON) and a silicon nitride film (SiN), and the interlayer insulating film preferably is a silicon oxide film (SiO2).
Preferably, the conductive layer includes a plug layer that fills the hole such that the plug layer is electrically connected to the high concentration impurity region, and an interconnection layer formed on the interlayer insulating film such that an electrical connection with the plug layer is established.
In this case, since the plug layer can be formed of a material that easily fills the hole, the electrical connection between the plug layer and the high concentration impurity region is further ensured. As a result, a semiconductor device capable of a high-speed operation with an even lower contact resistance can be provided.
Preferably, the semiconductor device is a static semiconductor memory device. In this case, an operation of a static semiconductor memory device at a higher speed becomes possible.
A semiconductor device according to another aspect of the present invention is provided with a semiconductor substrate, an interlayer insulating film, and a conductive layer. The semiconductor substrate has a conductive region. The interlayer insulating film has a hole reaching the conductive region of the semiconductor substrate. The conductive layer fills the hole such that an electrical connection with the conductive region is established. The hole is defined by a relatively high sidewall and a relatively low sidewall of the interlayer insulating film.
In a semiconductor device thus configured, since the hole is defined by a relatively high sidewall and a relatively low sidewall, the cross sectional area of the conductive layer can be increased by expanding the conductive layer above the low sidewall. Thus, the electrical resistance of the conductive layer becomes smaller, and thereby a semiconductor device capable of a high-speed operation can be provided.
Preferably, the semiconductor device is further provided with a gate electrode formed on the semiconductor substrate with a gate insulating film interposed therebetween, and a protective film covering the gate electrode and having an etching rate that is smaller than that of the interlayer insulating film when using a prescribed etchant.
In this case, the gate electrode is covered by the protective film having an etching rate smaller than the etching rate of the interlayer insulating film. Therefore, when forming a hole by etching the interlayer insulating film, the hole is mainly etched into the interlayer insulating film while the protective film is not as easily etched. Consequently, the hole does not reach the gate electrode covered by the protective film so that the conductive layer filling the hole and the gate electrode is prevented from becoming short-circuited.
Preferably, the protective film includes a nitride film and the interlayer insulating film includes an oxide film.
Further, the protective film preferably is at least one of a silicon oxynitride film and a silicon nitride film, and the interlayer insulating film preferably is a silicon oxide film.
The conductive region preferably includes a low concentration impurity region formed close to the gate electrode and having a relatively low impurity concentration and a high concentration impurity region formed at a location remote from the gate electrode and having a relatively high impurity concentration.
In this case, since the conductive region includes a high concentration impurity region having a relatively high impurity concentration, the high-speed operation of a semiconductor device formed by the gate electrode and the conductive region is achieved.
Preferably, the low concentration impurity region is formed by implanting an impurity into the semiconductor substrate using the gate electrode as a mask, and the high concentration impurity region is formed by implanting an impurity into the semiconductor substrate through a hole.
In this case, since the high concentration impurity region is formed by implanting an impurity into the semiconductor substrate through a hole, the bottom of the hole forms the high concentration impurity region. Since the conductive layer is formed by filling the hole, the conductive layer is electrically connected to the high concentration impurity region having a relatively high impurity concentration. As a result, the contact resistance between the conductive layer and the high concentration impurity region can be reduced, thereby achieving a high-speed operation of a semiconductor device.
Preferably, the conductive layer includes a plug layer filling a hole such that the plug layer is electrically connected to the high concentration impurity region, and an interconnection layer formed on an interlayer insulating film such that an electrical connection with the plug layer is established.
In this case, the electrical connection between the plug layer and the high concentration impurity region can be ensured by forming the plug layer with a material that easily fills the hole. As a consequence, the contact resistance becomes even smaller so that a high-speed operation of a semiconductor device becomes possible.
Preferably, the interlayer insulating film covering the gate electrode has a sidewall that is relatively low in height.
Moreover, the interlayer insulating film covering the gate electrode preferably has a sidewall that is relatively high in height.
Furthermore, the semiconductor device preferably is a static semiconductor memory device. In this case, a static semiconductor memory device capable of a high-speed operation can be provided.
A method of manufacturing a semiconductor device according to one aspect of the present invention includes the following steps of:
(1) forming a gate electrode on a semiconductor substrate with a gate insulating film interposed therebetween;
(2) implanting an impurity into the semiconductor substrate using the gate electrode as a mask to form a pair of low concentration impurity regions having a relatively low impurity concentration and being spaced apart from one another on a surface of the semiconductor substrate;
(3) forming a protective film covering the gate electrode and the semiconductor substrate;
(4) forming an interlayer insulating film covering the gate electrode and the protective film and having an etching rate greater than that of the protective film when a prescribed etchant is used;
(5) etching the interlayer insulating film with the condition that the etching rate of the interlayer insulating film is greater than that of the protective film to expose the protective film, and thereafter etching the protecting film with the condition that the etching rate of the protective film is greater than that of the interlayer insulating film to form in the interlayer insulating film a hole reaching a low concentration impurity region;
(6) implanting an impurity into the semiconductor substrate through the hole to form a high concentration impurity region having a relatively high impurity concentration within the low concentration impurity region;
(7) depositing a conductive material on the interlayer insulating film so as to fill the hole; and
(8) etching the conductive material while leaving the conductive material within the hole to form a conductive layer electrically connected to the high concentration impurity region.
According to this method, a high concentration impurity region is formed by implanting an impurity through the hole so that the bottom of the hole forms the high concentration impurity region. Thus, the hole and the surface of the high concentration impurity region connected through the hole do not shift out of position. Since the conductive layer is formed such that an electrical connection with the high concentration impurity region is established, the increase in contact resistance between the conductive layer and the high concentration impurity region can be prevented. As a result, a semiconductor device capable of a high-speed operation can be provided.
Preferably, the step of forming a conductive layer includes etching back the entire surface of the conductive material while leaving the conductive material within the hole to form a plug layer electrically connected to the high concentration impurity region, and forming an interconnection layer on the interlayer insulating film such that an electrical connection with the plug layer is established.
In this case, since the plug layer is formed by the etchback of the entire surface, the hole is positively filled with the plug layer. Consequently, no contact failure arises between the plug layer and the high concentration impurity region. Thus, a semiconductor device that is highly reliable and capable of a high-speed operation can be provided.
A method of manufacturing a semiconductor device according to another aspect of the present invention includes the following steps of:
(1) forming an interlayer insulating film on a semiconductor substrate having a conductive region;
(2) etching the interlayer insulating film to form in the interlayer insulating film a hole that reaches the conductive region and that is defined by a pair of sidewalls opposing one another;
(3) forming a resist covering one sidewall and filling the hole;
(4) removing a portion of the interlayer insulating film using the resist as a mask such that the other sidewall becomes lower in height;
(5) depositing a conductive material on the interlayer insulating film so as to fill the hole; and
(6) etching the conductive material while leaving the conductive material within the hole to form a conductive layer electrically connected to the conductive region.
According to this method, the conductive layer filling the hole is formed by removing a portion of the interlayer insulating film such that the other sidewall becomes lower. Therefore, the conductive layer is also formed on the interlayer insulating film in a region having the lowered height so that the cross section of the conductive layer can be increased. As a result, the electric resistance of the conductive layer becomes small, and a semiconductor device capable of a high-speed operation can be provided.
Preferably, the step of forming the conductive layer includes etching back the entire surface of the conductive material while leaving the conductive material within the hole to form a plug layer electrically connected to the conductive region, and forming an interconnection layer on the interlayer insulating film such that an electrical connection with the plug layer is established.
In this case, since the plug layer is formed by the etchback of the entire surface, the plug layer positively remains within the hole. Consequently, contact failure between the plug layer and the high concentration impurity region can be prevented. Thus, a semiconductor device that is highly reliable and capable of a high-speed operation can be provided.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.